This invention relates to an output circuit of a static random access memory circuit (hereinafter called a SRAM).
FIG. 4 is an output circuit of a conventional SRAM, and FIG. 5 is a timing chart of the output circuit in FIG. 4.
In FIG. 4, multiple memory cells arranged in a matrix in a memory cell block (not shown) each contain "1" or "0" data, and when one memory cell is selected by an address signal AD, the "1" or "0" data stored in that memory cell is read out. If the data being read out is a "1", the internal data S in FIG. 4 becomes a high level (an H level) and the internal data S becomes a low level (an L level). On the contrary, if the data being read out is a "0", the internal data S in FIG. 4 becomes an L level and the internal data S becomes an H level. An output control circuit 2 controls the gates of MOS FETs Q.sub.1 and Q.sub.2 of a data output circuit 1 according to the potential levels of the internal data S and S, and establishes the output Do at an H level or an L level. For example, when the internal data S is an H level and the internal data S is an L level (in other words, when the data stored in the selected memory cell is a "1"), both MOF FET gates Q.sub.1 and Q.sub.2 of the data output circuit 1 are set at an L level, and only the P-channel MOS FET Q.sub.1 is turned on, and the output Do is pulled up to an H level. On the contrary, when the internal data S is an L level and the internal data S is an H level (in other words, when the data stored in the selected memory cell is a "0"), both MOS FET gates Q.sub.1 and Q.sub.2 of the data output circuit 1 are set to an H level, and only the N-channel MOS FET Q.sub.2 is turned on, and the output Do is pulled down to an L level.
Therefore, when the address signal AD changes, the internal data S and S change from an H level to an L level or vice versa, and according to this change, the output control circuit 2 controls the gate potentials of MOS FETs Q.sub.1 and Q.sub.2 of the data output circuit 1, and the final output Do changes from an H level to an L level or vice versa. FIG. 5 shows such voltage changes.
In the conventional composition, however, the output Do changes largely from an H level (.perspectiveto.Vcc) to an L level (.perspectiveto.0 V), or from an L level (1/30 V) to an H level (.perspectiveto.Vcc). Generally, since the load connected to the output terminal of the SRAM has an extremely high capacity, if the potential change of the output Do is large, the transition time until the output Do settles at a stable value of an H level or an L level is long, and the reading operation of the SRAM cannot be increased in speed. Besides, since the output Do voltage changes by a large amount, a large momentary current flows through MOS FETs Q.sub.1 and Q.sub.2 of the output circuit 1.